Testing and fault isolation in semiconductor integrated circuits (IC's) has traditionally required a visual scan of the potentially faulty locations on the chip. Probes are utilized after a visual scan has been performed on the chip using a microscope. Such a visual scan over large portions of a 75,000 to 100,000 gate IC chip is extremely tedious and time consuming, and the results cannot be guaranteed.
If an error arises in a circuit, it is often impossible to isolate the exact location of the malfunctioning element. Testing procedures which have been employed to test ICs include transmitting data through the circuit and reading data output from the circuit. One problem with this technique is that all gates may not be exercised properly. That is, a two input NAND gate having one input zero will always output a value of one regardless of the state of the other input. Thus the integrity of the entire chip cannot be easily evaluated because the multitude of internal states cannot be determined based solely on output signals from the IC.
Prior testing methods performed testing on the chip and, based on the output from the chip, a visual scan was performed back through all paths leading to an output location determined to be faulty during the testing. While some areas on the chip can be ruled out as not containing faults using these methods, evaluation of IC chips using visual techniques is still necessary over a large portion of the chip.
Improving the testing time required for IC chips requires isolation of the faults on a chip to as small an area as possible. The cause of the fault may then be quickly determined if a small enough area can be isolated. Ideally, a single location should be isolated so that the cause of the failure can be visually determined with little time or effort.